1. Field of the Invention
The invention relates to a circuit arrangement.
2. Description of the Background Art
A circuit arrangement is made, for example, with a bridge configuration shown in FIG. 1. Circuit arrangements of this type cause an adjustment of the gate-source voltage of the Field-effect transistor M in such a way that the same voltage drop occurs across the drain-source path as across the reference resistor R.
Balancing circuits of the type shown in FIG. 1 are operated in a relatively small operating point, i.e., at low drain-source voltage drops, as occur also during normal MOS resistor operation outside balancing, for example, during use as a controllable resistor in a digital-to-analog converter.
A possible way to reduce the aforementioned balancing error is to select a relatively large operating point, i.e., higher drain-source voltage drops during balancing, so that the relative part of the offset voltage causing the balancing error becomes smaller. As a result, the balancing becomes more precise.
The ratio of the resistance value of the MOS resistor to the reference resistor depends on the manufacturing process selected for the fabrication of the MOS resistor, on the temperature, and on other parameters, which is why the balancing result cannot be applied in a simple way to the small operating point used for normal operation.